Author Name
Sravani Yerukala, Mahaboob Basha S, Chakrapani T, Ahmed Basha S, Suvarna K
Abstract
The Verilog-based FPGA accelerator AEKA, which implements an area-efficient Karatsuba polynomial multiplier for Ring-Binary-LWE post-quantum cryptography (PQC), is shown in this project. By reducing the amount of multiplications needed for polynomial operations, the design minimizes the use of DSP slices, LUTs, and registers on FPGA platforms by utilizing the divide-and-conquer Karatsuba algorithm. AEKA achieves high throughput and low area-delay product by combining time-multiplexing and pipelining, making lightweight PQC possible on resource-constrained devices like embedded systems and the Internet of Things. Xilinx Vivado is used to fully implement and verify the accelerator at the circuit level. When compared to traditional polynomial multipliers, simulation and synthesis results show notable gains in resource consumption and operational efficiency. For FPGA-base post-quantum cryptography, AEKA offers a workable, fast, and small solution that permits safe, lightweight cryptographi