Abstract
Multiprocessor System-on-Chip (MPSoC) architectures are widely used in high-performance computing, embedded systems, and real-time applications. A key challenge in MPSoC design is efficient communication between processing elements through shared bus architectures. Arbitration algorithms play a critical role in managing bus access, impacting performance, power consumption, and fairness. This paper presents an efficient arbitration algorithm designed to optimize latency, bandwidth utilization, and power efficiency while maintaining fairness in shared bus architectures. The proposed algorithm is evaluated through simulations and compared with existing arbitration schemes.